In the packaging of electronic devices and in particular of integrated circuits, the number of leads required for electrical communication with the device has grown substantially. At one time, leads exiting a device package were provided by a lead frame. As shown in FIG. 1, pads on the silicon chip (commonly called a die) were bonded to leads, 3, that ultimately protruded from the device package using thin wires between the pad and the package lead. These wires, 4, were attached to the pad and lead respectively by ultrasonic ball and wedge bonds. The geometry of such a packaging approach and the wire connection required, severely limits the number of external leads available and increases both the complexity and difficulty of the packaging approach, in general.
To improve on the lead frame configuration, solder bump flip chip approaches have been implemented. The silicon die has electrical contacts provided by solder balls attached generally in a regular array to one major surface of the die. Thus as shown in the plan view (not to scale) of a die (FIG. 2), the solder balls or bumps (generally denominated a ball grid array) are arranged in a regular matrix configuration. This array is then mated with a complementary array on a package substrate. On one side of the package substrate is a solder pad array whose surfaces align with the bumps of the die to which contact is desired. The opposing major surface of the substrate similarly has a solder ball array generally of a lower density than that of the array mating with the die. For example, typical high density arrays on the die are 100×100 arrays while substrate arrays for external connection on the opposing side of the substrate are typically 45×45 configurations. The interconnect between the more dense array mating with the die and the less dense array for external connection is produced generally by using multi-levels (often up to eight) of metal runner interconnects formed in the substrate much like the multi-level interconnects on the IC device itself except typically using a design rule on the order of 200 μm. The use of solder bumps substantially reduces the capacitance and inductance usually associated with the wire bond approach, significantly speeds the packaging process, and provides a much larger array of external interconnections to the internal die.
Although solder bump flip chip technology offers many advantages, the difference in the material of the die (e.g. a silicon based structure) and the material of the package substrate (e.g. a polymer based structure) presents challenges. One substantial problem results from the difference in the coefficient of thermal expansion between the die and the substrate. Generally, for common, high density devices presently available, it is not unusual that operating temperatures between 80 to 90° C. and in some cases 110 to 120° C. are produced. Since the coefficient of thermal expansion for silicon is two to three ppm/° C. and that for typical plastic substrates is 15 to 23 ppm/° C., during operation the substrate dimensions change significantly relative to that of the die. The mating solder bumps between the substrate and the die thus undergo substantial strain and, in the absence of an expedient to reduce such strain, the cumulative strain often leads to solder joint failure.
Typically, a material denominated an underfill composition is introduced between the die and the substrate so that it surrounds and physically but not electrically interconnects the mating solder bumps. Thus, as shown in FIG. 3, the die, 31, and the substrate, 32, are connected by solder bumps, 33. Underfill material, 34, surrounds the solder bumps and produces a physical communication between the substrate and the die. Generally, the underfill material is chosen to be relatively rigid, i.e. has an elastic modulus at room temperature of at least 2 MPa. The rigidity of the underfill material in essence produces a monolithic structure encompassing the die and the substrate and accordingly significantly reduces the stress on the mating solder bumps. In the presence of a rigid underfill material the mismatch induced stresses and strains on the solder bumps are reduced. As a result, solder bump failure is substantially mitigated for many devices. Nevertheless as the size of the die increases, the strain on the mating solder bumps, and especially the outermost periphery of such bumps, also increases as does the interfacial strain between the underfill and the die. As solder bump grid arrays with pitches less than 230 μm and with dies with largest dimensions greater than 15 mm are contemplated, the challenge for underfill materials has become difficult to meet. In particular, the extremely stiff materials required to preserve solder bump integrity are capable of causing the die itself to fracture or causing irreparable damage to the substrate itself as the substrate expands.
For next generation devices with dies having at least one of its dimensions 15 mm or more and thus typically having in excess of 3500 solder bumps between the substrate and the die with a pitch generally smaller than 230 μm, the stress generated is substantial. (A die has a dimension of 15 mm or more if a side of the smallest rectilinear polygon in which the die can be inscribed is 15 mm or more.) New characteristics for the underfill material are required to meet the demands of this next generation. Yet the characteristics that yield an adequate underfill material are uncertain.
Additionally, the underfill materials are generally polymers such as epoxies that are filled with materials such as glass spheres. The glass spheres are introduced to control the material properties. As solder bump grid arrays become larger and pitches become smaller, the thickness of the underfill materials becomes proportionately smaller. Accordingly, not only are different physical demands placed on underfill materials but the dimensions of the filler particles must also be sized accordingly. However, a change in such size, again, causes a change of the properties of the overall underfill composition. Thus identification of a suitable underfill material for dies having large dimension so that solder bump integrity is maintained without failure of the die itself has become an even more challenging problem. Accordingly, even though a very large number of materials are available for potential use as an underfill (see “Materials for Electronic Packaging—Polymers for Electronic Packaging” in Electronic Packaging and Interconnection Handbook, Charles A. Harper, Ed., New York: McGraw-Hill, 2000, pp. 1-57) and even though a plethora of materials are adequate for smaller dies, finding a material adequate for the next generation is a difficult problem.